As semiconductor devices such as logic and memory devices continue to scale to smaller dimensions, the use of conventional processing and materials to fabricate semiconductor devices is increasingly problematic. In some cases conventional polysilicon/silicon oxide gates used to build field effect transistors (FETs) are being replaced with metal gates and a high dielectric constant gate oxide. The source/drain and/or channel regions of a transistor may be changed to accommodate the performance targets for very small transistors.
In0.53Ga0.47As is a promising alternative material to silicon for fabricating n-type FET (n-FET) devices because of the very high room temperature electron mobility of In0.53Ga0.47As, reported to exceed 104 cm2/V-s. Little work has been undertaken to optimize the ohmic contacts to this material, a factor in determining overall device performance, especially as device size shrinks. As device size continues to shrink, the total series resistance has an increasingly negative effect on the FET drive current, where the series resistance can be mitigated by minimizing the resistance of the contacts to the source/drain regions. The contact resistivity of ˜5×10-8Ω cm2 or lower has been shown as a threshold to meet the electrical targets of NFETs at the 5 nm technology node using compound semiconductor n-type devices. This range of contact resistivity in turn entails concentrations of active dopants of ˜5×1019/cm3 or greater. To date such high concentrations have not been accomplished using ion implantation. The use of in-situ doping during growth of a semiconductor film has resulted in better levels of activation, while low film quality and unintentional doping remain challenges to this approach. In view of the above, satisfactory approaches to fabricating highly doped compound semiconductors are lacking. With respect to these and other considerations the present improvements are provided.